(1) Field of the Invention
This invention relates to a method of fabricating semiconductor devices using dual damascene processes to form plugs in the via holes composed of various high etch rate materials and bottom anti-reflection coating (BARC) materials.
(2) Description of Related Art
Related Prior Art background patents will now be described in this section.
U.S. Pat. No. 6,057,239 entitled “Dual Damascene Process Using Sacrificial Spin-on Materials” granted May 2, 2000 to Wang et al. shows a dual damascene process with a sacrificial plug. The dual damascene process includes the steps of forming a contact hole in an oxide layer disposed above a semiconductor substrate, disposing a layer of anti-reflective coating material on top of the oxide layer and in the contact hole, and partially etching the layer of anti-reflective coating material and the oxide layer to form the wiring trough. The partial etching step includes the steps of spin coating photoresist on top of the anti-reflective coating material, exposing the photoresist through a mask containing a pattern of the wiring trough, developing the photoresist to expose portions of the anti-reflective coating material, dry etching the exposed portions of the anti-reflective coating material to expose portions of the oxide layer, and wet etching the exposed portions of the oxide layer to form the wiring trough.
U.S. Pat. No. 6,268,283 B1 entitled “Method for Forming Dual Damascene Structure” granted Jul. 31, 2001 to Huang teaches a dual damascene process with a resist cap in the dual damascene opening. A via opening of the dual damascene structure is formed in a dielectric layer. A non-conformal cap layer is then formed on the substrate before the step of defining the photoresist layer. The non-conformal cap layer only covers the top region of the trench but does not fill the trench. A patterned photoresist layer is then formed on the substrate followed by an etching procedure so as to form a trench. The photoresist layer is then removed. The trench and via opening are filled with a conductive layer. Thereafter, redundant portions of the conductive layer are removed by a planarization process.
U.S. Pat. No. 6,033,977 entitled “Dual Damascene Structure” granted Mar. 7, 2000 to Gutsche et al. discloses a dual damascene process with a sacrificial plug. The method for manufacturing a dual damascene structure includes the use of a sacrificial stud and provides a defined edge on the interface between the conductive line openings and the via openings.
U.S. Pat. No. 5,635,423 entitled “Simplified Dual Damascene Process for Multi-level Metallization and Interconnection Structure” granted Jun. 3, 1997 to Huang et al. shows a semiconductor device containing an interconnection structure having a reduced inter-wiring spacing produced by a modified dual damascene process. In one embodiment, an opening for a via is initially formed in a second insulating layer above a first insulating layer with an etch stop layer between layers. A larger opening for a trench is then formed in the second insulating layer, while simultaneously extending the via opening through the etch stop layer and first insulating layer. The trench and via are then simultaneously filled with conductive material.
U.S. Pat. No. 6,096,655 entitled “Method for Forming Vias and Trenches in an Insulation Layer for a Dual Damascene Multilevel Interconnection Structure” granted Aug. 1, 2000 to Lee et al. discloses dual damascene processes for multilevel interconnection using a method for forming trenches and vias in the inter-insulation without etching out the inter-insulation layer. A thick sacrificial layer is first deposited and reversed etched to form sacrificial pillars forming the vias and sacrificial bridges forming the trenches. The sacrificial layer can be any material (insulator, semiconductor, or metal), provided it can be easily patterned and selectively removed later over the inter insulator layer. Thereafter, a low-k inter-insulation layer is deposited around the sacrificial pillars and bridges. It is these sacrificial pillars and bridges that are etched away leaving behind vias and trenches in the inter-insulation layer. In a preferred embodiment, a silicon film, either amorphous or polycrystalline, is used as the sacrificial layer.
U.S. Pat. No. 5,920,790 entitled “Method of Forming a Semiconductor Device Having Dual Inlaid Structure” granted Jul. 6, 1999 to Wetzel et al. teaches a dual damascene method for forming a semiconductor device that includes providing a substrate having a metal interconnect, depositing a via interlevel dielectric (ILD) layer over the substrate and the metal interconnect, and then etching the via ILD layer to form a via over the metal interconnect. This is then followed by depositing a trench ILD layer over the via ILD layer and the via, etching the trench ILD layer to form a trench. Finally, metal is deposited so as to fill the via and the trench, and provide electrical connection with the metal interconnect.